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4-channel, lvds, dual-output, laser diode driver with oscillator ad9665 rev. e information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2010 analog devices, inc. all rights reserved. features dual, current-controlled output current sources with 4 input channels ttl-selectable output stable on-chip oscillators with independent frequency and amplitude control ttl- or lvds-selectable write channel enables negative logic independent ttl oscillator enables positive logic 170 ma minimum output current for the read channel 510 ma minimum output current for write channel 1 330 ma minimum output current for write channel 2 165 ma minimum output current for write channel 3 950 ma typical total output current typical rise time/fall time of 0.8 ns low power consumption single 5 v power supply (10%) applications dvd-r, dvd+r, dvd-rw, dvd+rw, dvd-ram supercombo drives magneto-optical (mo) drives laser diode current switching general description the ad9665 is a laser diode driver for high performance cd-rw and dvd recordable drives. it includes four channels for four different optical power levels: the read channel generates a continuous output power level, whereas channel 1, channel 2, and channel 3 can be used as write channels that can be controlled with an lvds or ttl interface. the wxdis and rdis pins are active low logic. the oscen pin is controlled by an active high ttl signal. all active channels are summed at the output where write channel 1 can contribute at least 325 ma output current, and write channel 2 and write channel 3 can contribute at least 250 ma and 150 ma, respectively. the level of the output current is set by an external resistor, which converts this voltage into a current at the wxset pin. an on-chip oscillator is provided to allow output current modulation and to reduce laser-mode hopping. four external resistors permit the setting of two distinct values for the frequency and swing of the oscillator. the oscillator can output up to 100 ma p-p of current (push-pull oscillator) with a frequency range of 200 mhz to 500 mhz. functional block diagram write channel 3 write channel 2 write channel 1 read channel oscillator output a oscen rdis w1disn w1dis w1set w2disn w2dis w2set w3disn w3dis w3set rset output b ld1 ld2 f adj1 f adj2 a adj1 a adj2 ins outsel enable 05269-001 figure 1. 4-channel, lvds, laser driver block diagram 05269-050 *ttl active low notes 1. the exposed pad should be connected to ground. v dd n/c oscen outsel fadj1 fadj2 aadj1 aadj2 ins v dd ld1 ld1 gnd ld2 ld2 v dd ad9665 lfcsp 5mm 5mm (not to scale) w3dis* gnd w2dis* w1dis* gnd w3disn w2disn w1disn v dd v dd w3set w2set w1set rset enable rdis 24 23 22 21 1 2 3 32 20 19 18 17 9 10 11 12 13 14 15 16 4 5 6 7 8 31 30 29 28 27 26 25 figure 2. 4-channel, lvds, laser driver pin configuration
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ad9665 rev. e | page 2 of 16 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 5 esd caution .................................................................................. 5 typical performance characteristics ............................................. 6 logic table ......................................................................................... 8 applications ....................................................................................... 9 board layout ..................................................................................9 temperature considerations .......................................................9 shutdown supply current variation ....................................... 11 evaluation board ............................................................................ 12 schematic ..................................................................................... 12 operation ......................................................................................... 13 pin descriptions ......................................................................... 13 outline dimensions ....................................................................... 14 ordering guide .......................................................................... 14 revision history 8/ 10 rev ision e: initial version
ad9665 rev. e | page 3 of 16 specifications at 25c, v dd = 5 v, enable = 1, oscen = 0, f adj = 6.81 k, a adj = 5.76 k, v out = 2.5 v, i out = 50 ma (read), rdis = 0, unless otherwise specified. table 1. parameter conditions min typ max unit laser amplifier output current read channel output is sourcing, i in = 2 ma 170 190 ma output is sourcing, v out = 3.5 v, i in = 2 ma 150 170 ma output current write channel 1 output is sourcing, i in = 2 ma 510 540 ma output is sourcing, v out = 3.5 v, i in = 2 ma 450 480 ma output current write channel 2 output is sourcing, i in = 2 ma 330 360 ma output is sourcing, v out = 3.5 v, i in = 2 ma 290 320 ma output current write channel 3 output is sourcing, i in = 2 ma 165 185 ma output is sourcing, v out = 3.5 v, i in = 2 ma 145 165 ma total output current (see figure 11 ) all channels sourcing, i in = 1.45 ma 875 950 ma all channels sourcing, v out = 3.5 v, i in = 1.45 ma 775 850 ma output current linearity error read channel or write channel 3 1 ?1.5 0.4 +1.5 % write channel 1 2 or write channel 2 3 ?1.0 0.2 +1.0 % write channel 1, v out = 3.5 v, i in = 2 ma 4 ?15 ?9 % best-fit current gain read channel 1 85 105 115 ma/ma write channel 1 2 265 300 335 ma/ma write channel 2 3 165 200 225 ma/ma write channel 3 1 80 100 110 ma/ma best-fit current offset read channel or write channel 3 1 ?7 ?2 +4 ma write channel 1 2 ?17 ?3 +11 ma write channel 2 3 ?11 ?1 +8 ma i in input impedance (r in ), all channels r in to gnd, i out = 0 ma 140 200 260 i out current output noise f = 300 mhz 100 pa/hz i out supply sensitivity, (psrr) read mode v dd = 5 v 10% 3.5 %/v i out supply sensitivity, (psrr) write mode i out = 100 ma, 50 ma read channel, 50 ma any write channel, v dd = 5 v 10% 3.5 %/v i out temperature sensitivity, read mode 175 ppm/c i out temperature sensitivity, write mode i out = 100 ma (50 ma read channel, 50 ma write channel 1) 150 ppm/c i out = 100 ma (50 ma read channel, 50 ma write channel 2) 390 ppm/c i out = 100 ma (50 ma read channel, 50 ma write channel 3) 350 ppm/c laser amplifier ac spec ifications write rise time i out = 50 ma (read channel), 150 ma (write channel 1) 5 0.75 0.95 ns i out = 65 ma (read channel), 375 ma (write channel 1), v dd = 5 v, v out = 3.5 v 6 0.8 1.3 ns i out = 50 ma (read channel), 100 ma (write channel 2) 5 0.6 0.8 ns i out = 50 ma (read channel), 50 ma (write channel 3) 5 0.55 0.75 ns write fall time i out = 50 ma (read channel), 150 ma (write channel 1) 7 0.55 0.75 ns i out = 65 ma (read channel), 375 ma (write channel 1), v dd = 5 v, v out = 3.5 v 8 0.4 0.6 ns i out = 50 ma (read channel), 100 ma (write channel 2) 7 0.55 0.75 ns i out = 50 ma (read channel), 50 ma (write channel 3) 7 0.45 0.65 ns i out on propagation delay (lvds mode) logic at 50% of final value to i out at 50% of final value 5.2 ns i out off propagation delay (lvds mode) logic at 50% of final value to i out at 50% of final value 6.3 ns disable time enable 50% h-l to i out at 50% of final value 3.8 ns enable time enable 50% l-h to i out at 50% of final value 5.5 ns output switching time outsel 50% to i out at 50% of final value 3 ns oscillator specifications oscillator frequency oscen = 1 280 315 340 mhz oscillator amplitude oscen = 1 50 ma p-p oscillator temperature coefficient oscillator amplitude, oscen = 1 60 a p-p/c oscillator frequency, os cen = 1 195 khz/c
ad9665 rev. e | page 4 of 16 parameter conditions min typ max unit disable time oscillator oscen 50% h-l to i out at 50% of final value, oscen = 1 2 ns enable time oscillator oscen 50% l-h to i out at 50% of final value, oscen = 1 4 ns logic specifications ins = 1 (lvds mode) minimum differential input voltage magnitude 100 mv maximum differential input voltage magnitude 600 mv valid input voltage relative to gnd 0 2.4 v outen logic hi threshold temperature stabilized 2.0 v logic lo threshold temperature stabilized 0.8 v supply current 9 enable oscen rdis w1dis 10 w2dis 10 w3dis 10 ins = 1 (lvds mode) power down 0 0 1 1 1 1 8.6 ma inputs disabled, read enabled 1 0 0 1 1 1 26 ma inputs disabled, oscillator enabled 1 1 1 1 1 1 46 ma read mode, oscillator enabled 11 1 1 0 1 1 1 54 ma i out = 50 ma write mode 11 1 0 1 0 0 0 49 ma i out = 150 ma (50 ma write channel 1, write channel 2, write channel 3) ins = 0 (ttl mode) power-down 0 0 1 1 1 1 9.5 ma inputs disabled, read enabled 1 0 0 1 1 1 23 ma inputs disabled, oscillator enabled 1 1 1 1 1 1 43 ma read mode, oscillator enabled 11 1 1 0 1 1 1 51 ma i out = 50 ma write mode 11 1 0 1 0 0 0 43 ma i out = 150 ma (50 ma write channel 1, write channel 2, write channel 3) operating conditions supply voltage range 4.5 5.5 v operating temperature range ?25 +85 c 1 output linearity, offset current, and gain are calculated using the best-fit metho d at 30 ma, 60 ma, and 90 ma. the transfer f unction is i out = (i in gain) + i os . 2 output linearity, offset current, and gain are calculated using the best-fit method at 90 ma, 120 ma, and 150 ma. the transfer function is i out = (i in gain) + i os . 3 output linearity, offset current, and gain are calculated using the best-fit metho d at 60 ma, 90 ma, and 120 ma. the transfer function is i out = (i in gain) + i os . 4 output linearity is calculated using the best-fit metho d, which is calculated at 90 ma, 120 ma, and 150 ma, extrapolated to i in = 2 ma. 5 measured electrically fr om 10% to 90% of fina l value. sharp diodegh06550b2b (see figure 14). 6 measured electrically from 10% to 90% of final value. mitsubishi diodeml101j26. r l = 0.66 (see figure 14). 7 measured electrically fr om 90% to 10% of fina l value. sharp diodegh06550b2b (see figure 14). 8 measured electrically from 90% to 10% of final value. mitsubishi diodeml101j26. r l = 0.66 (see figure 14). 9 see the shutdown supply current var iation section for mo re information. 10 wxdis = 0 means channel is off re gardless of mode: ttl or lvds (see table 3). wxdis = 1 means channel is on regardless of mode : ttl or lvds (see table 3). 11 the value specified does not include the output current.
ad9665 rev. e | page 5 of 16 absolute maximum rat ings table 2. parameter range supply voltage (+v dd ) pins 10, 11, 17, 23, 32 6 v input pins pins 12, 13, 14, 15 2.2 ma pins 1, 2, 5, 6, 7, 8, 9, 16, 24, 29, 30 ? 0.8 v to +v dd internal p ower dissipation 1 5 mm 5 mm, 32 - lead, pad - up lfcsp 2 w operating temperature range ? 25 c to +85 c storage temperature range ? 65 c to +150 c 1 power dissipation is specified on semistandard 4 - layer board. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affe ct device reliability. esd caution
ad9665 rev. e | page 6 of 16 typical performance characteristics 05269-003 f adj resistance (k?) 14 0 2 4 6 8 10 12 oscillator frequency (mhz) 0 700 600 500 400 300 200 100 a adj = 5.76k? figure 3 . oscillator frequency vs. f adj frequency (mhz) 600 200 250 300 350 400 450 500 550 oscillator amplitude (ma p-p) 70 60 50 40 30 20 10 0 read (50ma) read (50ma) and write 3 (50ma) read (50ma) and write 2 (50ma) read (50ma) and write 1 (50ma) a adj = 5.76k? 05269-020 figure 4 . oscillator amplitude vs. frequency 05269-006 frequency (mhz) 1000 0.1 1 10 100 current noise (na/ hz) 0 2.5 2.0 1.5 1.0 0.5 out 2 out 1 figure 5. i out current noise 05269-004 a adjust resistance (k?) 14 0 2 4 6 8 10 12 oscillator amplitude (ma p-p) 0 200 175 150 125 100 75 50 25 f adj = 6.81k? read (50ma) read (50ma) and write 3 (50ma) read (50ma) and write 2 (50ma) read (50ma) and write 1 (50ma) figure 6 . oscillator amplitude vs. a adj i out current (ma dc) 100 80 90 0 10 20 30 40 50 60 70 oscillator amplitude (ma p-p) 70 30 35 40 45 50 55 60 65 05269-021 a adj = 5.76k? f adj = 6.81k? figure 7 . oscillator amplitude vs. i out - dc 05269-012 frequency (mhz) 600 100 200 300 400 500 distortion (dbc) ?20 ?30 ?40 ?50 ?60 ?70 ?80 second harmonic third harmonic fourth harmonic fifth harmonic figure 8 . oscillator distortion vs. frequency
ad9665 rev. e | page 7 of 16 05269-008 temperature (c) 100 ?40 ?20 0 20 40 60 80 amplitude (ma p-p) 30 60 55 50 45 40 35 read write 3 write 2 write 1 a adj = 5.76k? f adj = 6.81k? figure 9 . oscillator amplitude vs. temperature input current (ma) output current (ma) 1250 0 250 500 750 1000 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 05269-030 v dd = 5v v out = 2.5v temperature = 25c read total i out write 1 write 2 write 3 figure 10 . output current vs. input current for each channel, v out = 2.5 v 1000 0 0 2.0 input current for each channel (ma) total output current (ma) 800 600 400 200 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 v dd = 5v temperature = 25c i in = i in_rd = i in_wr1 = i in_wr2 = i in_wr3 v out = 3v v out = 3.5v v out = 2.5v v out = 2v 05269-011 figure 11 . total i out vs. i in 05269-010 temperature (c) 100 ?40 0 ?20 20 40 60 80 frequency (mhz) 300 330 320 325 315 310 305 a adj = 5.76k? f adj = 6.81k? figure 12 . oscillator frequency vs. temperature input current (ma) output current (ma) 1250 0 250 500 750 1000 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 05269-031 v dd = 5v v out = 3.5v temperature = 25c read total i out write 1 write 2 write 3 figure 13 . output current vs. input current for each channel, v out = 3.5 v ad9665 read 200? 4.32k? v in _rd wr1 200? 4.32k? v in _wr1 wr2 200? 4.32k? v in _wr2 wr3 200? 4.32k? v in _wr3 w1_p +5v r t 100? w1_n r t 100? r t 100? w2_p w2_n w3_p w3_n wr3 enable wr2 enable wr1 enable rd enable i out _1 ld_1 r l 3.4? r s 46.4? 50? r term 50? scope i out _2 ld_2 r l 3.4? r s 46.4? 50? r term 50? scope 05269-015 ins +5v outsel figure 14 . electrical lvds pulse response schematic
ad9665 rev. e | page 8 of 16 logic table table 3 . 05269-051 outsel h = ld1 output l = ld2 output ins h = lvds l = ttl oscen h = oscillator on l = oscillator off ttl use lvds + input enable outsel oscen rdis w1dis w1disn w2dis w2disn w3dis ins w3disn osc ld1 ld2 l x x x x x x x x x x x off off h l l l h x h x h l x off off i rset 100ma/ma h l h l h x h x h l x on off i rset 100ma/ma + i osc (f adj2 + a adj2 ) h l h h l x h x h l x on off i w1set 300ma/ma + i osc (f adj2 + a adj2 ) h l h h h x l x h l x on off i w2set 200ma/ma + i osc (f adj2 + a adj2 ) h l h h h x h x l l x on off i w3set 100ma/ma + i osc (f adj2 + a adj2 ) h l h h h x h x h l x on off i osc (f adj2 + a adj2 ) (not recommended) h l l l h l h l h h l off off i rset 100ma/ma h l h l h l h l h h l on off i rset 100ma/ma + i osc (f adj2 + a adj2 ) h l h h l h h l h h l on off i w1set 300ma/ma + i osc (f adj2 + a adj2 ) h l h h h l l h h h l on off i w2set 200ma/ma + i osc (f adj2 + a adj2 ) h l h h h l h l l h h on off i w3set 100ma/ma + i osc (f adj2 + a adj2 ) h l h h h x h x h h x on off i osc (f adj2 + a adj2 ) (not recommended) h h l l h x h x h l x off h h h l h x h x h l x on h h h h l x h x h l x on h h h h h x l x h l x on h h h h h x h x l l x on h h h h h x h x h l x on off off off off off off i rset 100ma/ma i rset 100ma/ma + i osc (f adj1 + a adj1 ) i w1set 300ma/ma + i osc (f adj1 + a adj1 ) i w2set 200ma/ma + i osc (f adj1 + a adj1 ) i w3set 100ma/ma + i osc (f adj1 + a adj1 ) i osc (f adj1 + a adj1 ) (not recommended) h h l l h l h l h h l off h h h l h l h l h h l on h h h h l h h l h h l on h h h h h l l h h h l on h h h h h l h l l h h on h h h h h l h l h h l on off off off off off off i rset 100ma/ma i rset 100ma/ma + i osc (f adj1 + a adj1 ) i w1set 300ma/ma + i osc (f adj1 + a adj1 ) i w2set 200ma/ma + i osc (f adj1 + a adj1 ) i w3set 100ma/ma + i osc (f adj1 + a adj1 ) i osc (f adj1 + a adj1 ) (not recommended)
ad9665 rev. e | page 9 of 16 applications the ad9665 uses the current at one or more of its four inputs, rset, w1set, w2set, and w3set, and generates an output current proportional to the sum of the input currents. the read channel has a typical gain o f 105 ma/ma, write channel 1 has a typical gain of 300 ma/ma, write channel 2 has a typ ical gain of 200 ma/ma, and write channel 3 has a typical gain of 100 ma/ma. the input impedance of all the channels is typically 200 ?. in most cases, a voltage output dac can be used to drive these channels. in this case, a series resi s tance should be placed between each of the dac channels and the respective input on the ad9665. these resistances should be selected to scale the desired maximum output current for each channel with an appropriate voltage from the dac wit h out excessively loading it. board layout due to the fast rise and fall time (<1 ns) required for the operation of high speed drives, trace lengths ca r rying high speed signals, such as r dis an s11 measurement of a piece of flexible printed circuit board (fpc) can show the inductance associated with that section of the fpc. in , w1dis, w2dis, and w3dis, and the output current should be kept as short as possible to minimize series inductance. a decoupling capacitor should be located near each v dd pin, and the ground return for the cathode of the laser diode should be kept as short as possible. table 4 , an s11 measurement of two different pieces of a 19 mm (0.75 in) fpc was taken. the first piece is a single layer of an fpc with 0.5 ounce copper and 25.4 micron (1 mil) thick kapton ? and coverlay. the second piece is an fpc with 2 layers of 0.5 o unce co p per and 25.4 micron (1 mil) thick ka p ton and coverlay. table 4 . inductance of fpc s11 l, nh @ 10 mhz l, nh @ 300 mhz single - layer fpc 8.8 8.5 double - layer fpc 4.3 4.2 as indicated by the measurement results, using two layers of copper in an fpc can reduce inductance by over 50%. using the basic circuit equation dt di lv = it can be seen that increasing the amplitude of a current step in creases the voltage drop across the inductor. for example, on the single - layer fpc, a 200 ma pulse with a rise time of 1 ns generates a voltage drop of 1.86 v, assuming an additional 0.5 nh of inductance due to the laser diode itself. increase this cu r rent to 250 ma, and the voltage drop is greater than 2.3 v. add this to the ~2 v of operating voltage that is required for the laser diode, and voltage headroom can become a pro b lem if operating on a 5 v supply. because the di/dt term seems to be a system requirement, l is the only contrib u tor that can be changed when trying to reduce the voltage drop. decreasing the inductance of the fpc can be do ne by either making the trace wider or by making it shorter. because the di s tance from the laser diode driver (ldd) to the laser diode is fixed, using a wider trace is the only option. this can be accomplished by changing from a single - layer fpc design to a double - layer fpc design. this a d ditional layer allows the full width of the fpc from the ldd to the laser diode to be used for the drive current, while the bo t tom layer can be used entirely for the return path (see figure 15). laser diode top trace bottom trace single-layer fpc i diode i diode double-layer fpc i diode i diode via 05269-016 figure 15 . single - layer and double - layer flexible printed circuit boards temperature consider ations the ad9665 is available in a 32 - lead lfcsp with an exposed heat pad on top of the package. using a 4 - layer jedec standard test bo ard, the ja of this package was determined without any ex ternal heat sink attached to the exposed pad . this board is made of fr4, is 1.60 mm thick, and consists of four copper layers. the two internal layers are solid copper (1 oz/in 2 or 0.35 mm thick). the two surface layers (containing the comp o nent and back side traces) use 2 oz/in 2 (0.70 mm thick) of copper. this method of constru c tion yields a ja for the ad9665 of approximately 110c/w. an integrated circuit di s sipating 500 mw and packaged i n a n lfc sp, while operating in an amb i ent environment of 85c, would have an internal junction temperature of approx i mately 140c. 85c + 0.5 w 110c/w = 140c this junction temperature is within the maximum reco m mended operating junction temperature of 150c. t his can be improved by a t taching an external heat sink to the exposed heat pad of the package. of course, this is not a realistic method for moun t ing a laser diode driver in an optical storage device. in an actual applic a tion, the laser diode driver would most likely be mounted to a flexible circuit board. the ja of a system is highly depend ent on the board layout, material, and heat sink. the user must consider these cond i tions carefully.
ad9665 rev. e | page 10 of 16 some of the circuitry of the ad9665 can be used to monitor the int ernal junction temperature. the ad9665 uses a combination of diodes and transistors to protect it from electrostatic discharge (esd). all input pins have a diode between them and ground, with the anode connected to ground and the cat h ode connected to the p articular input pin. the base - emitter junction of a pnp transistor is used for esd protection for each pin to v dd . the collector is electrically co n nected to the substrate of the die (see figure 16 ). the base - emitter junction of t his transistor can be used to monitor the internal die temperature of the ic. using a 10 v source at the enable pin to forward - bias the base - emitter junction and a 1 m ? resistor to limit the current, a 2- point measurement can be used to calculate the junc tion temperature of the ic. because the enable pin (enable) needs to be high for normal operation, the ad9665 can be operated normally with the 10 v applied through the 1 m ? resi s tor. for this experiment, v1 and v2 were measured between the en able pin (p in 16) and the closest v dd pin (pin 17). 5v 10v 1m? v1, v2 ? + v dd enable i be gnd r s i dd ad9665 05269-017 figure 16 . junction temperature measurement circuit the most important aspect of measuring junction temperature on the ad9665 is that only one variable in the system is changed at a time. in this case, the only variable is the amount of power being dissipated by the ad9665. therefore, the amb i ent temperature should be held constant. for example, to measure the junction temperature of the ad9665 while operating at 60c ambient, the ambien t temperature must be held constant for both the initial measur e ment, v1, and the final measurement, v2. this is true because of the relationship between temperature and v be . for the process with which the ad9665 is fabr i cated, the change in v be (v be ) is related to the die temperature by ? 1.9 mv/c (note the negative coefficient). therefore, die te m perature is directly related to ambient temperature and the power diss i pated. while the power to the ad9665 is disconnected, the ad9665 should be allowed to reach thermal equili b rium (at the desired ambient temperature). with all channels turned off such that i out = 0 ma, measure v1 as shown in figure 16 (note the pola r ity). the second point of the 2 - point measurement is obtained whe n the ad9665 is operated under load, for example, while driving a laser. before taking the measurement, the ad9665 must be allowed ad e quate time to reach a thermal equilibrium. as seen in figure 16 , the ad9665 has a finite parasit ic resistance (r s ) between v dd (pin 17) and the base of the pnp tra n sistor. this resistance is typically 120 m?. because the goal of the e x periment is to measure v be of the transistor, the voltage drop across this resistance must be taken into account to get an acc u rate representation of the actual v be . this voltage drop varies depending on the output current of the ad9665 operating under load. therefore, the actual supply current (i dd ) must be measured for each mea s urement. v drop = i dd r s so the resul ting v be can be found as v be = ( v2 + v drop2 ) ? ( v1 + v drop1 ) for increasing temperature, this result should be negative. from v be , the final junction temperature is determined by cmv/ 1.9 ? += be a j v tt from the resulting temperature rise in addition to the measured power dissipation, the thermal resistance from the junction to ambient can be calculated as p d = v dd i dd ? v load i load d a j p tt ? = ja
ad9665 rev. e | page 11 of 16 shutdown supply curr ent variation the ad9665 defaults to ttl input mode when the enable pin is tied low (enable = 0), regardless of the position of the ins pin. because of this, there can be additional supply current due to the applied vol t age on the read, write, or oscen enable pins, the cause of which is an inverter located on the ttl i n put ena ble pins (see figure 17 ). 05269-052 input output +v dd gnd figure 17 . inverter circuit voltages close to gnd or v dd are not sufficient to turn on both transistors. however, as voltages vary from these extremes, sig nificant current ca n flow. figure 18 shows how the power - down current varies with voltage applied on the read, write, or oscen enable pins. therefore, to ensure the lowest possible shutdown current, the read, write, and oscen voltages should be tie d to either 0 v or 5 v. 05269-053 ttl voltage on read and write channels (v) power-down supply current (ma) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0 16 12 8 4 5.0 valid ttl high valid ttl low nonvalid ttl region chip disabled figure 18 . read and write ttl enable voltage vs. supply current
ad9665 rev. e | page 12 of 16 evaluation board schematic w3disn 05269-018 v dd ld1 ld1 w3dis gnd v dd gnd ld2 ld2 rdis v dd v dd w3set w2set w1set rset enable gnd w2dis w1dis n/c oscen outsel f adj1 f adj2 a adj1 a adj2 ad9665 w3disn w2disn w1disn 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 ins v dd vdpos vdpos vdpos vdpos vdpos vdpos vdneg vdneg vdneg vdneg vdneg vdneg vdd vdd vd r22 dni w10 r15 6.81k? r16 6.81k? r17 5.76k? r18 5.76k? c1 0.1f vdd r21 dni r14 4.3k? r13 4.3k? r12 4.3k? r11 4.3k? enbl vdneg vdneg vdpos vdpos 5v c18 0.1f c17 0.1f c11 0.1f r10 0? vd w9 c5 dni c4 dni c3 dni c2 dni rset w1set w2set w3set vdd c12 10f r19 dni rdis w1dis w1disn w2dis w2disn w3dis oscen r20 dni r1 100? r2 100? r3 100? w1 w2 w3 w4 w5 w6 w8 w7 c13 10f c6 0.1f w11 vd c9 0.1f c8 0.1f c14 10f short, wide, and close short, wide, and close vdd r6 dni r7 dni c7 dni c10 dni r5 3.1? r8 3.1? d1 d2 r4 46.4? r9 46.4? ld1 ld2 outsel v dd + + + figure 19 . ad9665acpz - 32 evaluation board schematic
ad9665 rev. e | page 13 of 16 operation pin descriptions table 5 . pin no. mnemonic description 1 w3disn negative enable for write channel 3 (lvds mode only) 2 w3dis positive enable for write channel 3 (lvds mode), enable (ttl mode) 3, 4 gnd gnd 5 w2disn negative enable for write channel 2 (lvds mode only) 6 w2dis positive enable for write channel 2 (lvds mode), enable (ttl mode) 7 w1disn negative enable for write channel 1 (lvds mode only) 8 w1dis positive enable for write channel 1 (lvds mode), enable (ttl mode) 9 rdis enable for r channel (ttl only) 10 v dd 5 v supply and dc logic level for rdis and enable 11 v dd 5 v supply and dc logic level for rdis and enable 12 w3set input for write channel 3 (r in = 200 ?) 13 w2set input for write channel 2 (r in = 200 ?) 14 w1set input for write channel 1 (r in = 200 ?) 15 rset input for read channel (r in = 200 ?) 16 enable chip enable active high 17 v dd output stage supply, 5 v 18, 19 ld2 output 2 20 gnd gnd 21, 22 ld1 output 1 23 v dd output stage supply, 5 v 24 ins logic mode select (0 = ttl, 1 = lvds) 25 a adj2 amplitude resistor set for oscillator 2 26 a adj1 amplitude resistor set for oscillator 1 27 f adj2 frequency resistor set for oscillator 2 2 8 f adj1 frequency resistor set for oscillator 1 29 outsel output select (0 = ld2, 1 = ld1) 30 oscen oscillator enable active high 31 n/c no connection 32 v dd 5 v supply and dc logic level for oscen n/a epad the exposed pad should be connected to grou nd. the logic signals, wxdis, wxdisn , rdis , enable, ins, ou t sel, and oscen, can be driven with pulsed sources or can be set to a steady state level with jumpers. for steady state oper a tion, the logic level s for the wxdis and wxdisn evaluation board s are shipped with 100 ? termination resistors across the lvds inputs and without 50 ? resistors on the other logic traces. resistors r5 and r8 can be connected between ground and the cathodes of diode 1 and diode 2, respectively. to monitor diode current with an oscilloscope, a 3.1 ? resistor can be placed in each of these positions. the series 46.4 ? resistors at r4 and r9 present a 50 ? impedance to measurement equipment. this results in the oscill o scope displaying the diode current with a conversion fac tor of 1.558 mv/ma. if this capability is not d e sired, 0 ? resistors can be installed in the r5 and r8 positions. pins are set with voltages applied to the vdpos and vdneg pins on the evalu a tion board. for lvds mode (ins = 1), vdpos and vdneg should be at a level greater than 50 mv and less than 2.45 v (0.050 v < vdpos < 2.45 v and 0.05 v < vdneg < 2.45 v), with the differential voltage greater than 100 mv and less than 600 mv. for ttl o p eration (ins = 0), vdpos should be greater than 2.5 v and vdneg should be less than 0.8 v. under ttl operation, it may be convenient t o put vdpos at 5 v and vdneg at 0 v. the pin labeled 5 v is the logic level for ins and outsel. the v dd pins are connected together in the ic and can be connected to the same external supply. although they are all connected inte r nally, there must be a direct connection to each of these pins through their vector pins e x ternally, which are also labeled v dd . a jumper set to the right side of a 3 - lead connection applies the vdpos voltage to the applicable pin on the ic. a jumper set to the left side of a 3 - lead connection applies the vdneg vol t age.
ad9665 rev. e | page 14 of 16 outline dimensions * compliant to jedec standar ds mo-220 with exception to paddle orientation. f or prope r connection of the exposed pad, refer to th e pin configuration s ection of this data sheet. 09-18-2008-a 1 32 8 9 25 24 16 17 2.85 2.70 sq 2.55 0.50 0 .4 0 0.30 3.50 ref pin 1 indicator 5.00 bsc sq 4.75 bsc sq 0.45 bsc 0.20 min * exposed pad top view bottom view 0.80 max 0.65 typ coplanarity 0.05 0.20 ref 1.00 0.85 0.80 0.05 max 0.02 nom seating plane 12 max 0.30 0.23 0.18 0.60 max 0.60 max 0.50 bsc figure 20 . 32 - lead pad - up, lead frame chip scale package [lfcsp_vq] 5 mm 5 mm body, very th in quad (cp - 32 - 1) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ad9665acpz - reel ? 25c to +85c 32- lead, pad - up, lead frame chip scale pac k age [lfcsp_vq] cp -32 -1 ad9665acpz - reel7 ? 25c to +85c 32- lead, pad - up, lead frame chip scale pac k age [lfcsp_vq] cp -32 -1 1 z = rohs compliant part.
ad9665 rev. e | page 15 of 16 notes
ad9665 rev. e | page 16 of 16 notes ? 2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d05269 -0- 8/10(e)

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